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K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 1 document title 512k x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 1.0 1.1 1.2 1.3 remark preliminary history initial issue. 1. changed operating voltage 2.7v ~ 5.5v ? 3.0v ~ 5.5v data sheet 1999 1. added ce don?t care mode during the data-loading and reading 1. changed device name - km29w040at -> K9F4008W0A-TCB0 - km29w040ait -> k9f4008w0a-tib0 1.powerup sequence is added : recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences 2. ac parameter tclr(cle to re delay, min 50ns) is added. 3. ac parameter tar is devided into tar1, tar2 (before revision) (after revision) ale to re delay t ar 250 - ns ale to re delay(id delay) t ar1 20 - ns ale to re delay(read cycle) t ar2 250 - ns v cc wp high ? ? ~ 2.5v ~ 2.5v ? we 1 m draft date april 10th 1998 july 14th 1998 april 10th 1999 sep. 15th 1999 jul. 23th 2001 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.intl.samsungsemi.com/memory/flash/datasheets.html
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 2 512k x 8 bit nand flash memory the k9f4008w0a is a 512kx8bit nand flash memory. its nand cell structure provides the most cost-effective solution for digital audio recording. a program operation programs a 32-byte frame in typical 500 m s and an erase operation erase a 4k-byte block in typical 6ms. data in a frame can be read out at a burst cycle rate of 120ns/byte. the i/o pins serve as the ports for address and data input/output as well as for command inputs. the on-chip write controller automates the program and erase operations, including program or erase pulse repetition where required, and performs internal verification of cell data. the k9f4008w0a is an optimum solution for flash memory application that do not require the high performance levels or capacity of larger density flash memories. these application include data storage in digital telephone answering devices(tad) and other consumer applications that require voice data storage. general description features voltage supply: 3.0v~5.5v organization - memory cell array : 512k x 8 bit - data register : 32 x 8 bit automatic program and erase (typical) - frame program : 32 byte in 500 m s - block erase : 4k byte in 6ms 32-byte frame read operation - random access : 15 m s(max.) - serial frame access : 120ns(min.) command/address/data multiplexed i/o port low operation current (typical) - 10 m a standby current - 10ma read/ program/erase current reliable cmos floating-gate technology - endurance : 100k program/erase cycles package - 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) pin configuration vss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 vcc i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c gnd r/ b re ce vcc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44(40) tsop (ii) note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc, v ss or gnd inputs disconnected. pin description pin name pin function i/o 0 ~ i/o 7 data inputs/outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect gnd ground input r/ b ready/busy output v cc power v ss ground n.c no connection
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 3 figure 1. functional block diagram figure 2. array organization note : *(1) : x can be v il or v ih * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 3rd cycle a 16 a 17 a 18 x* (1) x* x* *x *x column address (a 0 -a 4 ) frame address (a 5 -a 6 ) row address (a 7 -a 11 ) block address (a 12 -a 18 ) 128bytes 4k rows (=128 blocks) 32 bytes 8 bit good block i/o 0 ~ i/o 7 1 frame = 32 bytes 1 row = 4 frames = 128 bytes 1 block = 32 rows = 4k bytes 1 device = 32bytes x 4frames x 32rows x 128blocks = 4mbits frame register 1 2 3 4 x-buffers 4m bit command nand flash array 32byte x 4frames x 4096rows y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers a 7 - a 18 a 0 - a 6 command ce re we cle ale wp i/o 0 i/o 7 the 1st block (4kb) 1block = 32 rows = 4k bytes
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 4 product introduction the k9f4008w0a is a 4m bit memory organized as 4096 rows by 1024 columns. a 256-bit data register is connected to memory cell arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. the memory array is composed of unit nand structures in which 8 cells are connected serially. each of the 8 cells reside in a different row. a block consists of the 32 rows, totaling 4096 unit nand structures of 8bits each . the array organization is shown in figure 2. the program and read operations are executed on a frame basis, while the erase operatio n is executed on a block basis. the memory array consists of 128 separately erasable 4k-byte blocks. the k9f4008w0a has addresses multiplexed into 8 i/o pins. this scheme not only reduces pin count but allows systems upgrades to higher density flash memories by maintaining consistency in system board design. command, address and data are all written through i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles. for byte-level addressing, the 512k byte physical space requires a 19-bit address, low row address and high row address. frame read and frame program require the same three address cycles fol- lowing by a command input. in the block erase operation, however, only the two row address cycles are required. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the k9f4008w0a. table 1. command sets caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 00h - reset ffh - o frame program 80h 10h block erase 60h d0h status read 70h - o read id 90h -
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 5 pin description command latch enable(cle) the cle input controls the path activation for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. address latch enable(ale) the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising ed ge of we with ale high. chip enable( ce ) the ce input is the device selection control. when ce goes high during a read operation the device is returned to standby mode. however, when the device is in the busy state during program or erase, ce high is ignored, and does not return the device to standby mode. write enable( we ) the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. read enable( re ) the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid t rea after the falling edge of re which also increments the internal column address counter by one. i/o port : i/o 0 ~ i/o 7 the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high- z when the chip is deselected or when the outputs are disabled. write protect( wp ) the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. ready/ busy (r/ b ) the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 6 dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions vcc = 3.0v ~ 3.6v vcc = 3.6v ~ 5.5v unit min typ max min typ max oper- ating current burst read cycle i cc1 trc=120ns, ce =v il , i out =0ma - 5 10 - 10 20 ma program i cc2 - - 5 10 - 10 20 erase i cc3 - - 5 10 - 10 20 stand-by current(ttl) i sb1 ce =v ih , wp =0v/v cc - - 1 - - 1 stand-by current(cmos) i sb2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 m a input leakage current i li v in =0 to 5.5v - - 10 - - 10 output leakage current i lo v out =0 to 5.5v - - 10 - - 10 input high voltage, all inputs v ih - 2.4 - v cc + 0.3 2.4 - v cc + 0.5 v input low voltage, all inputs v il - -0.3 - 0.6 -0.3 - 0.8 output high voltage level v oh i oh =-400 m a 2.4 - - 2.4 - - output low voltage level v ol i ol =2.1ma - - 0.4 - - 0.4 output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - 8 10 - ma absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in -0.6 to +7.0 v temperature under bias K9F4008W0A-TCB0 t bias -10 to +125 c k9f4008w0a-tib0 -40 to +125 storage temperature t stg -65 to +150 c recommended operating conditions (voltage reference to gnd, K9F4008W0A-TCB0 : t a =0 to 70 c, k9f4008w0a-tib0 : t a =-40 to 85 c) parameter symbol min typ. max unit supply voltage v cc 3.0 - 5.5 v supply voltage v ss 0 0 0 v
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 7 capacitance ( t a =25 c, vcc=5.0v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input / output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f4008w0a may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correct ion. parameter symbol min typ. max unit valid block number n vb 125 - 128 block program/erase characteristics parameter symbol min typ max unit program time t prog - 0.5 1 ms number of partial program cycles in the same frame nop - - 10 cycles block erase time t bers - 6 10 ms mode selection note : 1. x can be v il or v ih 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x sequential read & data output l l l h h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by ac test condition (K9F4008W0A-TCB0:t a =0 to 70 c, k9f4008w0a-tib0:t a =-40 to 85 c , v cc =3.0v ~ 5.5v unless otherwise noted) parameter value vcc=3.0v ~ 3.6v vcc=3.6v ~ 5.5v input pulse levels 0.4v to 2.6v 0.4v to 2.6v input rise and fall times 5ns input and output timing levels 0.8v and 2.0v output load 1 ttl gate and cl = 100pf
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 8 ac characteristics for operation note : 1. the time to ready depends on the value of the pull-up resistor tied r/ b pin. parameter symbol min max unit data transfer from cell to register t r - 15 m s ale to re delay(id delay) t ar1 20 - ns ale to re delay(read cycle) t ar2 250 - ns ce low to re low (id read) t cr 250 - ns cle to re delay t clr 50 - ns ready to re low t rr 100 - ns re pulse width t rp 60 - ns we high to busy t wb - 200 ns read cycle time t rc 120 - ns re access time t rea - 50 ns re high to output hi-z t rhz 0 30 ns ce high to output hi-z t chz - 50 ns re high hold time t reh 40 - ns output hi-z to re low t ir 0 - ns ce high to ready(in case of interception by ce at read) t cry - 100+tr(r/ b ) (1) ns re low to status output t rsto - 60 ns ce low to status output t csto - 70 ns we high to re low t whr 50 - ns re access time(read id) t whrid 100 - ns device resetting time (read/program/erase) t rst - 5/10/500 m s ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time t cls 50 - ns cle hold time t clh 50 - ns ce setup time t cs 50 - ns ce hold time t ch 50 - ns we pulse width t wp 60 - ns ale setup time t als 50 - ns ale hold time t alh 50 - ns data set-up time t ds 40 - ns data hold time t dh 20 - ns write cycle time t wc 120 - ns we high hold time t wh 40 - ns
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 9 identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nforma- tion regarding the invalid block(s) is called as the invalid block information. the invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. devices with invalid block(s) have the same quality level or as devices with all va lid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the performance of valid block(s) because it is iso- lated from the bit line and the common source line by a select transistor. the system design must be able to mask out the invali d block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correction. nand flash technical notes all device locations are erased(ffh) except locations where the invalid block information is written prior to shipping. since th e invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore , the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid blo ck table via the following suggested flow chart(figure 1). any intentional erasure of the original invalid block information is prohibite d. * check "ffh" on the 1st and 2nd page figure 1. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 10 error in program or erase operation k9f4008w0a technical notes (continued) failure mode detection and countermeasure sequence block erase failure read after erase --> block replacement frame program failure status read after program --> block replacement single bit program failure ("1" --> "0") block verify after program --> block replacement during erase operation ; when the error occurs after an erase operation, prevent future accesses to this bad block (again by creating a table within the system or other appropriate scheme.) over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. to improve the efficiency of mem- ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 11 system interface using ce don?t-care. ce we t wp t ch t cs start add.(3cycle) 80h data input ce cle ale we i/o 0 ~ 7 data input ce don?t-care ? ? 10h for a easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant savings in power consumption. start add.(3cycle) 00h ce cle ale we i/o 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea (max. 60ns) ce re i/o 0 ~ 7 timing requirements : if ce is is exerted high during sequential data-reading, the falling edge of ce to valid data(tcea) must be kept greater than 60ns. figure 3. program operation with ce don?t-care. figure 4. read operation with ce don?t-care. must be held low during tr.
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 12 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle ce we cle ale i/o 0 ~ 7 a 0 ~a 7 a 8 ~a 15 a 16 ~a 18 t cls t cs t clh t ch t wp t als t alh t ds t dh t cls t cs t wc t wc t wp t wp t wh t wh t als t alh t ds t dh t ds t dh t ds t dh t wp
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 13 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 31 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp * burst read cycle after frame access (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 dout dout dout t rc t rp t rea t rr t rhz* t rea t reh t rea t rhz* t rhz ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 14 * status read cycle ce we cle re i/o 0 ~ 7 70h status output t clr t clh t rea t wp t ch t ds t dh t rsto t ir t rhz t chz t whr t csto read operation (read one frame) ce cle r/ b i/o 0 ~ 7 we ale re busy dout n dout n+1 dout n+2 dout n+3 dout 32 column address row address t wb tar2 t r t chz t rc t rhz t rr 00h a 0 ~ a 7 a 8 ~ a 15 a 16 ~ a 18 ? ? ?
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 15 read operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy dout n dout n+1 dout n+2 dout n+3 row address t wb tar2 t chz t r t rr address column 00h a 0 ~a 7 a 8 ~a 15 a 16 ~a 18 ce cle r/ b i/o 0 ~ 7 we ale re program operation 80h 70h i/o 0 din n din din 10h 31 n+1 a 0 ~ a 7 a 16 ~ a 18 a 8 ~ a 15 sequential data input command column address row address 1 up to 32 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t wc t wc t wc t wb t prog ? ? ? ? ?
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 16 ce cle r/ b i/o 0 ~ 7 we ale re block erase operation 60h a 16 ~a 18 a 8 ~a 15 auto block erase setup command erase command doh busy t wb t bers block address ?
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 17 device operation frame read upon initial device power up or after excution of reset(ffh) command, the device defaults to read mode. this operation is also i ni- tiated by writing 00h to the command register along with three address cycles. the three cycle address input must be given for access to each new frame. the read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the d ata registers in less than 15 m s(t r ). the cpu can detect the completion of this data transfer(t r ) by analyzing the output of r/ b pin. once the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing re with ce staying low. high to low transitions of the re clock output the data starting from the selected column address up to the last column address within the frame(column 32). figure 3. read operation start add.(3cycle) 00h busy(seek time) a 0 ~a 7 & a 8 ~a 18 data output(sequential) seek time 0 31 ce cle ale re we i/o 0 ~ 7 r/ b
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 18 frame program the device is programmed on a frame basis. the addressing may be done in random order in a block. a frame program cycle consist of a serial data loading period in which up to 32 bytes of data must be loaded into the device, and a nonvolatile programming p eriod in which the loaded data is programmed into the appropriate cells. the sequential data loading period begins by inputting the frame program setup command(80h), followed by the three cycle address input and then sequential data loading. the bytes other than those to be programmed do not need to be loaded. the frame program confirm command(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the programming process. the internal write controller automatically executes the algorithms and t imings necessary for program and verify, thereby freeing the cpu for other tasks. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6 ) of the status register. only the read status command and reset command are valid while programming is in progress. when the frame program is complete, the write status bit(i/o 0 ) may be checked. the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read sta tus command mode until another valid command is written to the command register. figure 4. frame program operation 80h a 0 ~a 7 & a 8 ~a 18 i/o 0 ~ 7 r/ b address & data input 32 byte data 10h frame program while the frame size of the device is 32 bytes, not all the bytes in a frame have to be programmed at once. the device supports par- tial frame programming in which a frame may be partially programmed up to 10 separate program operations. the program size in each of the 10 partial program operations is freely determined by the user and do not have to be equal to each other or to any p reset size. however, the user should ensure that the partial program units within a frame do not overlap as "0" data cannot be changed to "1" data without an erase operation. to perform a partial frame program operation, the user only writes the partial frame data t hat is to programmed. just as in the standard frame program operation, an 80h command is followed by start address data. however, only the partial program data need be divided when programming a frame in 10 partial program operations. figure 5. example of dividing a frame into 10 partial program units fa a2 43 cb 81 28 e0 2a d5 - - - - - - 32 b5 7d 6f aa e1 d7 c0 single frame 1st partial program start address (00h) 2nd partial program start address (04h) 3rd partial program start address (06h) : : : : : : 9th partial program start address (18h) 10th partial program start address (1fh) 10th partial frame program data 9th partial frame program data 3rd partial frame program data : : : : : : 2nd partial frame program data 1st partial frame program data t prog
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 19 figure 6. block erase operation block erase the erase operation is done 4k bytes(1 block) at a time. block address loading is accomplished in two cycles initiated by an era se setup command(60h). only address a 12 to a 18 are valid while a 8 to a 11 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required. 60h block add. : a 8 ~a 18 i/o 0 ~ 7 r/ b address input(2cycle) d0h read status the device contains a status register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. after writing 70h command to the command register, a read cycle outputs t he contents of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remai ns in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the required read command(00h) should be input before serial page read cycle. table2. read status register definition i/o # status definition i/o 0 program "0" : successful program "1" : error in program i/o 1 reserved for future use "0" i/o2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected t bers
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 20 figure 7. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during the read, program or erase mode, the reset operation will abort these operation. in the case of reset during program or erase operat ions, the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the device e nters the read mode after completion of reset operation as shown table 3. if the device is already in reset state a new reset command will not be accepted to by the command register. the r/ b pin transitions to low for t rst after the reset command is written. reset com- mand is not necessarily for normal device operation. refer to figure 7 below. after power-up after reset operation mode read read ffh i/o 0 ~ 7 r/ b table3. device status t rst
K9F4008W0A-TCB0, k9f4008w0a-tib0 flash memory 21 figure 9. read id operation ce cle i/o 0 ~ 7 ale re we 90h add. input(1cycle) dout(ech) dout( a4h ) a 0 ~a 7 :"0" maker code device code t cea t whr t ar1 t rea t clr
package dimensions flash memory 22 ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a frame program, erase or read seek completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command register or a random read is begin after address loading. it returns to high when the internal controller has finished the operation. the pi n is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and cur- rent drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 10). its value can be determined by the following guidance. v cc r/ b open drain output device gnd where i l is the sum of the input currents of all devices tied to the r/ b pin. rp t r , t f [ s ] i b u s y [ a ] rp(ohm) fig 10 rp vs tr ,tf & rp vs ibusy ibusy tr rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp(min) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf 2.0v tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 96 tf 189 290 381 4.2 4.2 4.2 4.2 3.3 1.65 1.1 0.825 0.8v
package dimensions flash memory 23 figure 11. ac waveforms for power transition data protecttion the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences as shown in figure 11. the two step command sequence for program/erase provides additional software protection. ~ 2.5v ~ 2.5v v cc wp high ? ? we 10 m s ? ?
package dimensions flash memory 24 package dimensions unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop2 - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )

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